1. Field of the Invention
This invention relates generally to non-volatile memory devices having a floating gate . More particularly, the present invention relates to a new and novel reading circuitry and method for performing program verify, erase verify and over-erase-correction verify operations on a selected memory core cell in an array of EPROM, EEPROM, or Flash EEPROM memory core cells which uses only a single reference cell so as to reduce the amount of trimming time required during manufacturing.
2. Description of the Prior Art
As is generally well-known in the art, non-volatile memory devices using a floating gate for the storage of charges thereon such as EPROMs (electrically programmable read-only memories), EEFROMs (electrically, erasable programmable read only memories) or Flash EEPROMs have emerged in recent years. In such a conventional Flash EEPROM memory device, a plurality of such one-transistor memory may be formed on a P-type semiconductor substrate in which each cell is comprised of an n+ drain region and an n+ source region both formed integrally within the substrate. A relatively thin gate dielectric layer is interposed between a top surface of the substrate and a conductive polysilicon floating gate. A polysilicon control gate is insulatively supported above the floating gate by a second dielectric layer. A channel region in the substrate separates the drain and source regions.
As is well-known, the charge of the floating gate of the one-transistor cell is dependent upon the number of electrons contained in the floating gate. During the programming mode, electrons are added to the floating gate of the cell so as to increase its threshold voltage. The term xe2x80x9cthresholdxe2x80x9d refers to a gate-to-source voltage that must be applied between the gate and the source of the cell in order to cause it to conduct. During the erase mode, electrons are removed from the floating gate of the cell so as to decrease its threshold voltage. In programmed state, the threshold voltage of a cell is typically set at greater than +6.5 volts, while the threshold voltage of a cell in an erased state is typically limited below +3.0 volts.
In order to determine whether the cell has been programmed or not, the cell is read by applying a small positive voltage to the control gate between the +3.0 and +6.5 volt range, typically +5.0 volts, with the source region held at a ground potential (0 volts) and the drain held at a potential between +1 to +2 volts. If the transistor cell conducts or is turned-on, a current will flow through the transistor representing a xe2x80x9c1xe2x80x9d bit or erased state. On the other hand, if the transistor cell does not conduct or is turned-off no current will flow through the transistor representing a xe2x80x9cxe2x80x9d bit or programmed state.
FIG. 1 is a simplified functional block diagram of a conventional semiconductor integrated memory circuit device 100 which includes a Flash EEPROM memory array 102 formed of a plurality of memory core cells MC11-NCnm (each being formed as described above). The plurality of memory cells NC11-MCnm are arranged in an nxc3x97m matrix on a single integrated circuit chip. Each of the memory cells is comprised of one of the array core transistors QP11 through QPnm which function as a memory transistor for storing data xe2x80x9c1xe2x80x9d or xe2x80x9cxe2x80x9d therein. Each of the core transistors has its drain connected to one of the plurality of bit lines BL-BLM. All of the sources of the array core transistors are connected to a common array ground potential VSS. Each of the core transistors also has its control gate connected to one of the plurality of word lines WL-WLN.
The memory circuit device 100 further includes a row address decoder 104, a column address decoder 106, and a Y-pass gate circuit 108. The row address decoder 104 selects one of the corresponding word lines WL-WLn in the memory core cell array 102 in response to row address signals Ai. At the same time, the column decoder 106 selects one of the corresponding bit lines Bl-BLm in response to column address signals Aj. The Y-pass gate circuit 108 connects the corresponding array bit lines to a sensing or reading circuitry 110.
In order to determine the state of a selected memory core cell, the reading circuitry 110 includes a sense amplifier functioning as a comparator which receives a core current signal from a bit line on its one input and receives a reference current signal from a reference line on its other input. In this manner, the core current signal corresponding to a core current is compared with the reference current signal corresponding to a reference current from a reference cell. The result on the output of the comparator indicates whether the selected memory core cell is storing a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
With reference to FIG. 2 of the drawings, there is shown a simplified schematic circuit diagram of certain portions of the memory circuit device 100 of FIG. 1 to explain how the program verify, erase verify, and over-erase-correction verify states of one selected array core transistor QP is determined. In particular, the reading or sensing circuitry 110 of FIG. 2 includes a comparator 120, a reference resistor 122 having a resistance value R2, a sense resistor 124 having a resistance value R1, a core transistor QP, and a plurality of reference transistors QR1-QR4. The comparator 120 is actually one of the sense amplifiers of FIG. 1.
The reference resistor 122 has its one end connected to a supply potential or voltage VCC, which is typically at +1.0 volts, and its other end connected to the non-inverting input of the comparator 120 at node A. The node A is also coupled to the drains of the reference transistors QR1-QR4 via the reference cell line REF and corresponding switches S1-S4. One end of the sense resistor 124 is also connected to the supply potential VCC, and the other end thereof is connected to the inverting input of the comparator 120 at node B. The node B is also connected to the drain of the core transistor QP via the selected bit line BL. As can be seen, the gates of the core transistor QP and the reference transistors QR1-QR4 are connected together and receive the same control gate voltage VG_SENSE via the selected word line WL.
During a normal Read mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR1 having a read threshold voltage RD_VT by closing the switch S1. During a program verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR2 having a program verify threshold voltage PGM_VT by closing the switch S2. During an erase-verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR3 having an erase-verify threshold voltage ERS_VT by closing the switch S3. During an over-erase-correction mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR4 having an over-erase-correction threshold voltage OEC_VT by closing the switch S4.
The various threshold voltages for the four reference cells QR1-QR4 are required to satisfy the following condition:
OEC_VT less than ERSxe2x80x94VT less than RDxe2x80x94VT less than PGMxe2x80x94VT
As will be noted from FIG. 3, the reference cell current from the four respective reference cells QR1-QR4 (each having a different reference threshold voltage) are plotted as a function of the control gate bias VG applied to the respective reference cells. Since the reference cells are identical to the array core cells, the plotted IDS curves A-D are parallel to each other and are also parallel to the IDS curve of an array core cell. Thus, the plotted curves A-D are only separated from one another by the differences in values of the their threshold voltages.
In order to determine whether the selected core cell QP is erase verified, the reference cell QR3 having the threshold ERS_VT will be used by closing the switch S3. When a bias voltage VG_SENSE is applied to the control gates of both the selected core cell QP and the reference cell QR3, the comparator 120 will effectively compare the core cell current ICELL with the reference cell current ERS_IREF. In order for the comparator to output a logic xe2x80x9c1xe2x80x9d indicative of the selected core cell QP being erase-verified, the core cell current ICELL is required to be larger than the reference cell current ERS_IREF.
With reference still to FIG. 3, it can be seen that if the core cell current ICELL is larger than the reference cell current ERS_IREF, then it will be also indeed larger than the reference cell current RD_IREF. Therefore, a selected core cell QP that has passed erase verify will likewise cause the comparator to output a logic xe2x80x9c1xe2x80x9d during the normal Read mode of operation where the reference cell QR1 having the threshold voltage RD_VT will be used by closing the switch S1 in order to produce the corresponding reference current RD_IREF. In other words, the core cell current ICELL will be greater than the reference cell current RD_IREF, which is less than the reference current ERS_IREF, since it is greater than the reference current ERS_IREF.
Based upon a similar analogy, in order to determine whether the selected core cell QP is program verified, the reference cell QR2 having the threshold PGM_VT will be used by closing the switch S2. When a bias voltage VG_SENSE is applied to the control gates of both the selected core cell QP and the reference cell QR3, the comparator 120 will effectively compare the core cell current ICELL with the reference cell current PGM_IREF. In order for the comparator to output a logic xe2x80x9c0xe2x80x9d indicative of the selected core cell QP being program-verified, the core cell current ICELL is required to be smaller than the reference cell current PGM_IREF.
With reference again to FIG. 3, it can be seen that if the core cell current ICELL is smaller than the reference current PGM_IREF, then it will be also indeed smaller than the reference cell current RD_IREF. Therefore, a selected core cell QP that has passed program verify will likewise cause the comparator to output a logic xe2x80x9c0xe2x80x9d during the normal Read mode of operation where the reference cell QR1 having the threshold voltage RD_VT will be used by closing the switch S1 in order to produce the corresponding reference current RD_IREF. In other words, the core cell ICELL will be smaller than the reference cell current RD_IREF, which is greater than the reference current PGM_IREF, since it is smaller than the reference current PGM_IREF.
In order to determine whether the selected core cell is over-erase-correction verified, the reference cell QR4 having a threshold voltage OEC_VT will be used by closing the switch S4. As will be noted from FIG. 3, in order to produce a current greater than zero when the bias voltage VG_SENSE=0V is being applied during the over-erase-correction verify mode of operation, it is required that the threshold voltage OEC_VT of the reference cell QR4 be set at less than 0V (negatively).
This prior reading circuitry 110 of FIG. 2 suffers from the disadvantages of several drawbacks. Firstly, in conjunction with the performing of the reading, erase verify, program verify, and over-erase-correction verify operations in the array of Flash EEPROM memory cells, there is required the task of trimming (programming) and verifying the threshold voltage of each of the four reference cells QR1-QR4. This trimming procedure involves the cycle of applying a program pulse to the reference cell, program verifying the reference cell, and applying another program pulse which is repeated over and over until the particular reference cell has been successfully trimmed to the different desired threshold voltages (e.g.,RD_VT, PGM_VT, ERS_VT, or OEC_VT). Thus, the trimming (setting) process is a very difficult and time-consuming task performed during fabrication of the memory devices which will increase the labor costs.
Secondly, the trimming of the reference cell QR4 to a negative threshold voltage is not desirable or convenient since it will create additional problems, such as requiring a negative supply voltage and/or other special testing equipment. Thirdly, since each reference cell (except for cell QR1) is storing either a positive or negative charge on its floating gate, they are unstable or susceptible to charge loss when there is a disturb. As a result, their threshold voltages will tend to change and thus the associated reference current IREF will be varied. It will be noted that the threshold voltage RD_VT of the reference cell QR1 is typically set near a neutral threshold voltage of UV_VT, which is defined as when there is neither a positive or negative charge added to the floating gate of the cell. Therefore, the closer the threshold voltage of the reference cell is to the neutral threshold voltage UV_VT, the more stable it will be.
Accordingly, there has been discovered by the inventor a new and novel reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of Flash EEPROM memory cells which overcomes the prior art problems. This is accomplished in the present invention by utilizing a single reference cell whose control gate bias voltage is varied to produce different reference current values.
Accordingly, it is a general object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which overcomes the disadvantages of the prior art.
It is an object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells so as to reduce the amount of trimming time required during manufacturing.
It is another object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which includes a single reference cell transistor having a fixed threshold voltage and whose control gate bias voltage is varied to produce different reference current values.
It is still another object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which includes means for generating a core cell drain current, means for generating reference currents corresponding to predetermined modes of operation, and comparator means for comparing the drain current and the reference currents in order to determine whether the selected core cell has passed program verify, erase verify, and over-erase-correction verify.
In a preferred embodiment of the present invention, there is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations.
A comparator is used for comparing a sensed voltage corresponding to the core cell drain current and a reference voltage corresponding to one of the different reference currents. The comparator generates an output signal which is at a high logic when the sensed voltage is less than the reference voltage and which is at a low logic level when the sensed voltage is higher than the reference voltage.